arm64支持128位页表 · v2

[mm: Add read-write accessors for vm_page_prot] Currently vma->vm_page_prot is safely read from and written to, without any locks with READ_ONCE() and WRITE_ONCE(). But with introduction of D128 page

[arm64/mm: Route all pgtable reads via ptval_get()] Define arm64 platform specific implementations for new pxdp_get() helpers. These resolve into READ_ONCE(), thus ensuring required single copy atomic

[arm64/mm: Route all pgtable writes via ptval_set()] Currently ptval_set() is defined as WRITE_ONCE() but this will change for D128 pgtable builds, for which WRITE_ONCE() is not sufficient for single

[arm64/mm: Route all pgtable atomics to central helpers] Route all cmpxchg() operations performed on various page table entries to a new ptval_cmpxchg_relaxed() helper. Similarly route all xchg() oper

[arm64/mm: Override read-write accessors for vm_page_prot] Override pgprot_read|write accessors using ptval_get|set providing required single copy atomic operation for vma->vm_page_prot. Cc:

[arm64/mm: Enable fixmap with 5 level page table] FEAT_D128 halves PTRS_PER_PXX thus shrinking the VA range coverage for each page table level. Hence in order to preserve all existing VA range configu

[arm64/mm: Enable pgtable geometry for FEAT_D128] Add build time support for FEAT_D128 page tables with a new Kconfig option i.e CONFIG_ARM64_D128. When selected, PTE types become 128 bits wide and PT

[arm64/mm: Enable pgtable descriptor for FEAT_D128] Enable pgtable descriptor fields and related accessors for FEAT_D128. First expand ptval_t as 128 bits, add all D128 specific pgtable descriptor fie

[arm64/mm: Enable 128 bit translation] All required changes to page table geometry and descriptor are now in place for D128 translation to be enabled. Since FEAT_D128 exclusively supports the permiss

[arm64/mm: Add an abstraction level for tlbi_op] From: Linu Cherian linu.cherian@arm.com With FEAT_D128, a new instruction aka TLBIP is being introduced for the TLB -by-range operations which has a

[arm64/mm: Enable TLBIP instruction based TLB flush] From: Linu Cherian linu.cherian@arm.com Add TLBIP instruction support for TLB flush operation updating all relevant macros as necessary. This en

[arm64/mm: Relax KASAN shadow alignment for FEAT_D128] D128 reduces the number of descriptors in each translation table, causing some VA size and page granule combinations that use two page table leve

[arm64/mm: Make ARM64_D128 selectable] All required changes are already in place including the TLBIP instruction support for enabling D128 translation. Just make this new ARM64_D128 user selectable, a

Provide a slimline configuration intended to be booted with ARM64_D128. Cc: Catalin Marinas catalin.marinas@arm.com Cc: Will Deacon will@kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: li