RISC-V 硬件断点观察点 · v8

[riscv: Introduce support for hardware break/watchpoints] [patchwork series v8] submitter=Himanshu Chauhan patches (8): [v8,1/8] riscv: Introduce support for hardware break/watchpoints [v8,2/8] ri

Add self test for riscv architecture. It uses ptrace to ptrace framework to set/unset break/watchpoint and uses signals to check triggers. Also add $(KHDR_INCLUDES) to CFLAGS for the riscv test build

Add support for the RISC-V PTRACE_GETHBPREGS and PTRACE_SETHBPREGS requests. A tracer can use these requests to read or program one hardware breakpoint or watchpoint slot at a time. Store the ptrace-

Add NT_RISCV_HW_BREAK and NT_RISCV_HW_WATCH. A tracer can use PTRACE_GETREGSET and PTRACE_SETREGSET to read or program the RISC-V hardware breakpoint and watchpoint slots. The regset layout uses fixe

Cover the new ptrace-based hardware breakpoint/watchpoint support added for riscv: exercise the PTRACE_GETREGSET/SETREGSET regset path as well as the raw PTRACE_GETHBPREGS/SETHBPREGS interface, alongs

Move get_insn() and __read_insn() out of traps_misaligned.c so breakpoint single-step code can share the instruction fetch logic. Add helpers to read GPR values and compute the next RISC-V PC for con

With mc/mc6 triggers, after handling breakpoint at current pc, there is no way to tell trigger to skip same breakpoint after the handler returns. This can cause loop of breakpoints at the same address

In the breakpoint signal handler test, a breakpoint is set on __test_function. Keep that helper as a real call target so the breakpoint has a stable address. The test also relies on the watched varia